In the ongoing narrative of Moore’s Law, the spotlight has long been on fabrication. Foundries race to shrink features, boost performance, and increase transistor density. But there is a quieter crisis unfolding on the design side of the equation. Today, chip designers are often ready with architectures that demand more than current fabs can deliver. When development at the design level accelerates faster than manufacturing capabilities, the real scaling problem begins. Erik Hosler, a semiconductor strategist who translates advanced technology into consumer-relevant outcomes, makes it clear that what matters most is not the geometry of a chip but the value it delivers in the hands of users.
This disconnect is creating new tension within the industry. Designers envision complex, high-performance chips packed with accelerators, memory stacks, and domain-specific architectures. However, fabricating these designs requires process technologies that are still catching up. As a result, engineers must often scale back, adjust, or delay implementation. The challenge is not that the design lacks innovation but that it cannot yet be built with the available manufacturing capabilities.
The Growing Divide
The scaling crisis is no longer about physical limits. It is about synchronization. While design tools, IP libraries, and architectural models have developed rapidly, the pace of physical process improvements has slowed. Feature size reduction is harder, more expensive, and increasingly limited by unpredictable chemical behaviors at the atomic scale.
It has created a mismatch between what designers want to build and what fabs can fabricate. Even the best ideas on paper must be filtered through the lens of manufacturability. Design rule constraints, yield optimization, and cost-per-die considerations all impose limits on what can go from simulation to silicon. In short, the bottleneck has shifted. It is no longer about patterning smaller transistors. It is about aligning ambitious designs with the realities of current process technologies.
When Design Leaps Ahead
Architectural development has not slowed down. In fact, it has accelerated. Designers are creating chips with vertically integrated memory, chiplet-based modularity, and AI acceleration blocks tailored to specific workloads. These advances are essential for modern applications like machine learning, edge computing, and real-time analytics.
But these designs often depend on ultra-fine routing, tight packaging tolerances, and extremely precise interconnects. If fabs are not yet equipped with the right tools, materials, or processes, the design must be scaled down or split across multiple chips, increasing latency and reducing efficiency.
The result is a compromise. Performance targets are adjusted. Cost and power consumption may rise. Time-to-market suffers. Innovation stalls not because ideas are lacking, but because fabrication is lagging behind design capability.
Consumer Experience as the Ultimate Measure
In a market driven by end-user expectations, a chip’s feature size is not the headline. Consumers care about what the chip enables, not how it was built. Whether it is seamless gaming, instant AI response, or longer battery life, the real measure of success is the experience, not the silicon geometry.
Erik Hosler observes, “This is because consumers don’t care what the feature size is inside a chip.” This insight reframes the crisis. If the consumer experience continues to improve, Moore’s Law is still effectively alive, even if transistor sizes plateau. But if scaling slows and experience stagnates, then it will feel like a collapse, regardless of how advanced the architecture may be. That places even greater importance on aligning design and manufacturing. If fabs cannot produce what designers envision, then the value never reaches the end user.
Bridging the Gap
To address this divide, the industry is exploring new ways to bring design and manufacturing into closer harmony. One solution is the co-optimization of design and process, often referred to as Design-Technology Co-Optimization (DTCO). In this model, designers work with foundries early in the development cycle to align expectations, define realistic design rules, and ensure manufacturability.
Another strategy is the use of digital twins. These simulation environments replicate fabrication processes so that designers can evaluate how their layouts will behave under real-world conditions. This predictive modeling helps reduce iterations and increases the likelihood that a design will work the first time it is taped out.
Packaging is also playing a larger role. With advanced 2.5D and 3D integration, designers can distribute functions across multiple dies, each built using the most suitable node. This chiplet approach allows for heterogeneous integration while minimizing risk.
Rethinking Performance Metrics
In a world where design is often ready before manufacturing is, traditional metrics like transistor count or node number are becoming less useful. Instead, performance-per-watt, workload efficiency, and system-level throughput are becoming the new benchmarks.
Designers optimize for these outcomes regardless of the underlying process node. That is why chips built on mature nodes can still deliver impressive results, and software optimization is becoming part of the performance equation. The race is no longer about who reaches the smallest feature size. It is about who can deliver the best experience, the most efficient solution, and the fastest path from concept to consumer.
Design-Fab Synchronization: The Next Frontier
Alignment between design and manufacturing will require more than technical solutions. It will require organizational and business model changes. Foundries are beginning to form tighter alliances with design tool vendors and IP developers to create end-to-end solutions that can support rapid development.
For example, some fabs are introducing early-access platforms where designers can experiment with new process nodes months before they are production-ready. Others are embedding machine learning into their EDA tools to flag layout features that may lead to yield issues.
The industry is also embracing ecosystem thinking. No single company, team, or tool can solve the coordination challenge alone. Open communication, shared modeling frameworks, and standardized design flows will be essential to build a future where design and fabrication grow in step.
When done right, this synchronization allows for smoother transitions to new nodes, faster design cycles, and better overall chip quality. It ensures that the progress happening in architecture does not outpace the ability to bring those ideas to life in silicon.
A New Definition of Progress
The real scaling crisis is not a technical failure. It is a coordination challenge. Chip design is sprinting ahead, while fabrication is working overtime to keep up. Rather than viewing this as a roadblock, the industry has an opportunity to build stronger bridges between imagination and implementation.
By aligning design tools, manufacturing roadmaps, and system goals, engineers can continue to deliver on the promise of progress, even if Moore’s Law, in its classic form, becomes more symbolic than literal.
The future of development will not be limited by how small we can go, but by how well we can connect the visions of chip designers with the realities of fabrication.
